MTech Digital Circuit And Logic Design syllabus for 1 Sem 2018 scheme 18ELD14

Module-1 Module-1 10 hours

Threshold Logic:

Introductory Concepts, Synthesis of Threshold Networks, Capabilities, Minimization, and Transformation of Sequential Machines: The Finite- State Model, Further Definitions, Capabilities.

Module-2 Module-2 10 hours

Fault Detection by Path Sensitizing, Detection of Multiple Faults, Failure-Tolerant Design, Quadded Logic, Reliable Design and Fault Diagnosis Hazards: Fault Detection in Combinational Circuits.

A d v e r t i s e m e n t
Module-3 Module-3 10 hours

Fault-Location Experiments, Boolean Differences, Limitations of Finite – State Machines, State Equivalence and Machine Minimization, Simplification of Incompletely Specified Machines.

Module-4 Module-4 10 hours

Structure of Sequential Machines:

Introductory Example, State Assignments Using Partitions, The Lattice of closed Partitions, Reductions of the Output Dependency, Input Independence and Autonomous Clocks, Covers and Generation of closed Partitions by state splitting, Information Flow in Sequential Machines, ELD ecompositions, Synthesis of Multiple Machines.

Module-5 Module-5 10 hours

State Identifications and Fault-Detection Experiments:

Homing Experiments, Distinguishing Experiments, Machine Identification, Fault Detection Experiments, Design of Diagnosable Machines, Second Algorithm for the Design of Fault Detection Experiments, Fault-Detection.