Faults in digital circuits:
Failures and Faults, Modeling of faults, Temporary Faults. (Text 1)
Logic Simulation:
Applications, Problems in simulation based design verification, types of simulation, The unknown logic values, compiled simulation, event-driven simulation, Delay models, Element evaluation, Hazard detection, Gate-level event-driven Simulation. (Text 2)
Test generation for Combinational Logic circuits:
Fault Diagnosis of digital circuits, Test generation techniques for combinational circuits, Detection of multiple faults in Combinational logic circuits. (Text 1)
Testable Combinational logic circuit design:
The Read-Muller expansion technique, Three level OR-AND-OR design, Automatic synthesis of testable logic.(Text 1)
Testable Combinational logic circuit design:
Testable design of multilevel combinational circuits, Synthesis of random pattern testable combinational circuits, Path delay fault testable combinational logic design, Testable PLA design. (Text 1)
Test generation for Sequential circuits:
Testing of sequential circuits as Iterative combinational circuits, state table verification, Test generation based on Circuit Structure, Functional Fault models, test Generation based on Functional Fault models. (Text 1)
Design of testable sequential circuits:
Controllability and observability, Ad-Hoc design rules for improving testability, design of diagnosable sequential circuits, the scan-path technique for testable sequential circuit design, Level Sensitive Scan Design(LSSD), Random Access Scan Technique, Partial scan, testable sequential circuit design using Nonscan Techniques, Cross check, Boundary Scan. (Text 1)
Built-In Self Test:
Test pattern generation for BIST, Output response analysis, Circular BIST, BIST Architectures. (Text 1)
Testable Memory Design:
RAM Fault Models, Test algorithms for RAMs, Detection of pattern-sensitive faults, BIST techniques for RAM chips, Test generation and BIST for embedded RAMs. (Text1)