Introduction: Design methodology – An introduction; IC technology options
Logic Design with Verilog: Structural models of combinational logic; Logic simulation, Design verification, and Test methodology; Propagation delay; Truth-Table models of Combinational and sequential logic with Verilog.
Logic Design with Behavioral Models: Behavioral modeling; A brief look at data types for behavioral modeling; Boolean-Equation – Based behavioral models of combinational logic; Propagation delay and continuous assignments; Latches and Level – Sensitive circuits in Verilog; Cyclic behavioral models of Flip-Flops and Latches; Cyclic behavior and edge detection; A comparison of styles for behavioral modeling; Behavioral models of multiplexers, encoders, and decoders; Dataflow models of a Linear- Feedback Shift Register; Modeling digital machines with repetitive algorithms; Machines with multi-cycle operations; Design documentation with functions and tasks; Algorithmic state machine charts for behavioral modeling; ASMD charts; Behavioral models of counters, shift registers and register files; Switch debounce, meta-stability and synchronizers for asynchronous signals; Design example
Synthesis of Combinational and Sequential Logic: Introduction to synthesis; Synthesis of combinational logic; Synthesis of sequential logic with latches; Synthesis of three-state devices and bus interfaces; Synthesis of sequential logic with flip-flops; Synthesis of explicit state machines; Registered logic; State encoding; Synthesis of implicit state machines, registers and counters; Resets; Synthesis of gated clocks and clock enables; Anticipating the results of synthesis; Synthesis of loops; Design traps to avoid; Divide and conquer: Partitioning a design.
Programmable Logic and Storage Devices: Programmable logic devices; storage devices;PLA; PAL; Programmability of PLDs; CPLDs; FPGAs; Verlog-Based design flows forFPGAs; Synthesis with FPGAs.