06CS33 Logic Design syllabus for CS


Part A
Unit-1 Digital Logic Combinational Logic Circuits 7 hours

Digital Logic: Overview of Basic Gates and Universal Logic Gates, AND-OR-Invert Gates, Positive and Negative Logic, Introduction to HDL 2 Hours Combinational Logic Circuits: Boolean Laws and Theorems, Sum-of-products Method, Truth Table to Karnaugh Map, Pairs, Quads, and Octets, Karnaugh Simplifications, Don’t Care Conditions, Product-of-sums Method, Product-of-sums Simplification, Simplification by Quine-McClusky Method, Hazards and Hazard Covers, HDL Implementation Models 5 Hours

Unit-2 Data-Processing Circuits 6 hours

Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD-to-Decimal Decoders, Seven-segment Decoders, Encoders, EX-OR gates, Parity Generators and Checkers, Magnitude Comparator, Read-only memory, Programmable Array Logic, Programmable Logic, Troubleshooting with a Logic Probe, HDL Implementation of Data Processing Circuits

Unit-3 Arithmetic Circuits 6 hours

Arithmetic Circuits: Binary Addition, Binary Subtraction, Unsigned Binary Numbers, Sign-Magnitude Numbers, 2’s Complement Representation, 2’s Complement Arithmetic, Arithmetic Building Blocks, The Adder-Subtractor, Fast Adder, Arithmetic Logic Unit, Binary Multiplication and Division, Arithmetic Circuits using HDL

Unit-4 Clocks and Timing Circuits Flip-Flops 7 hours

Clocks and Timing Circuits: Clock Waveforms, TTL Clock, Schmitt Trigger, Monostables with Input Logic, Pulse-forming Circuits 2 Hours Flip-Flops: RS Flip-flops, Gated Flip-flops, Edge-triggered RS, D, JK Flip-flops, Flip-flop timing, JK Master-slave Flip-flops, Switch Contact Bounce Circuits, Various Representations of Flip-flops, Analysis of Sequential Circuits, Conversion of Flip-flops – a synthesis example, HDL implementation of Flip-flop 5 Hours

Part B
Unit-5 Registers Counters 7 hours

Registers: Types of Registers, Serial In-Serial Out, Serial In-Parallel Out, Parallel In-Serial Out, Parallel In-Parallel Out, Applications of Shift Registers, Register Implementation in HDL 2 Hours Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus, Decade Counters, Presettable Counters, Counter Design as a Synthesis Problem, A Digital Clock, Counter Design Using HDL 5 Hours

Unit-6 Design of Sequential Circuit 7 hours

Design of Sequential Circuit: Model Selection, State Transition Diagram, State Synthesis Table, Design Equations and Circuit Diagram, Implementation using Read Only Memory, Algorithmic State Machine, State Reduction Technique, Analysis of Asynchronous Sequential Circuit, Problems with Asynchronous Sequential Circuits, Design of Asynchronous Sequential Circuit

Unit-7 D/A Conversion and A/D Conversion 6 hours

D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous A/D Conversion, A/D Techniques, Dual-Slope A/D Conversion, A/D Accuracy and Resolution

Unit-8 Digital Integrated Circuits 6 hours

Digital Integrated Circuits: Switching Circuits, 7400 TTL, TTL Parameters, TTL Overview, Open-collector Gates, Three-state TTL Devices, External Drive for TTL Loads, TTL Driving External Loads, 74C00 CMOS, CMOS Characteristics, TTL-to-CMOS Interface, CMOS-to TTL Interface

Last Updated: Tuesday, January 24, 2023