10CS33 Logic Design syllabus for CS


Part A
Unit-1 Digital Principles, Digital Logic 7 hours

Definitions for Digital Signals, Digital Waveforms, Digital Logic, 7400 TTL Series,
TTL Parameters The Basic
Gates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive and Negative Logic,
Introduction to HDL.

Unit-2 Combinational Logic Circuits 6 hours

Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs Quads, and Octets,
Karnaugh Simplifications, Don’t-care Conditions, Product-of-sums Method,
Product-of-sums simplifications, Simplification by Quine-McClusky Method, Hazards and Hazard
Covers, HDL Implementation Models.

Unit-3 Data-Processing Circuits 6 hours

Multiplexers, Demultiplexers, 1-of-16 Decoder,Encoders, Exclusive-or Gates,
Parity Generators and Checkers, Magnitude Comparator, Programmable Array Logic,
Programmable Logic Arrays, HDL Implementation of Data Processing Circuits

Unit-4 Clocks, Flip-Flops 7 hours

Clock Waveforms, TTL Clock, Schmitt Trigger,Clocked D FLIP-FLOP, Edge-triggered D FLIP-FLOP,
Edge-triggered JK FLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP,
Switch Contact Bounce Circuits, Various Representation of FLIP-FLOPs,
Analysis of Sequential Circuits, HDL Implementation of FLIP-FLOP

Part B
Unit-5 Registers 6 hours

Types of Registers, Serial In - Serial Out, Serial In - Parallel out,Parallel In - Serial Out,
Parallel In - Parallel Out, Universal Shift Register,Applications of Shift Registers,
Register Implementation in HDL

Unit-6 Counters 7 hours

Asynchronous Counters, Decoding Gates, Synchronous Counters,Changing the Counter Modulus,
Decade Counters, Presettable Counters,Counter Design as a Synthesis problem, A Digital Clock,
Counter Design using HDL

Unit-7 Design of Synchronous and Asynchronous Sequential Circuits 7 hours

Design of Synchronous Sequential Circuit: Model Selection, State Transition Diagram,
State Synthesis Table, Design Equations and Circuit Diagram,
Implementation using Read Only Memory, Algorithmic State Machine, State Reduction Technique.
Asynchronous Sequential Circuit: Analysis of Asynchronous Sequential Circuit,
Problems with Asynchronous Sequential Circuits, Design of Asynchronous Sequential Circuit,
FSM Implementation in HDL

Unit-8 D/A Conversion and A/D Conversion 6 hours

Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and Resolution,
A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous A/D Conversion,
A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution

Last Updated: Tuesday, January 24, 2023