15CSL37 Analog and Digital Electronics Laboratory syllabus for CS



A d v e r t i s e m e n t

Module-1 Laboratory Experiments: 0 hours

1. a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTPvalues and demonstrate its working.
b) Design and implement a Schmitt trigger using Op-Amp using a simulationpackage for two sets of UTP and LTP values and demonstrate its working.

Module-2 Laboratory Experiments: 0 hours

2. a) Design and construct a rectangular waveform generator (Op-Amp relaxationoscillator) for given frequency and demonstrate its working.
b) Design and implement a rectangular waveform generator (Op-Amp relaxationoscillator) using a simulation package and demonstrate the change infrequency when all resistor values are doubled.

Module-3 Laboratory Experiments: 0 hours

3. Design and implement an Astable multivibrator circuit using 555 timer for agiven frequency and duty cycle.
NOTE: hardware and software results need to be compared

Module-4 Laboratory Experiments: 0 hours

4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractorusing basic gates.

Module-5 Laboratory Experiments: 0 hours

5. a) Given a 4-variable logic expression, simplify it using Entered Variable Mapand realize the simplified logic expression using 8:1 multiplexer IC.
b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulateand verify its working.

Module-6 Laboratory Experiments: 0 hours

6. a) Design and implement code converter I)Binary to Gray (II) Grayto Binary Code using basic gates.

Module-7 Laboratory Experiments: 0 hours

7. Design and verify the Truth Table of 3-bit Parity Generator and 4-bit ParityChecker using basic Logic Gates with an even parity bit.

Module-8 Laboratory Experiments: 0 hours

8. a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truthtable.
b) Design and develop the Verilog / VHDL code for D Flip-Flop with positiveedgetriggering. Simulate and verify its working.

Module-9 Laboratory Experiments: 0 hours

9. a) Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and demonstrate its working.
b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulateand verify its working.

Module-10 Laboratory Experiments: 0 hours

10. Design and implement an asynchronous counter using decade counter IC tocount up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).

Module-11 Laboratory Experiments: 0 hours

11. Generate a Ramp output waveform using DAC0800 (Inputs are given to DACthrough IC74393 dual 4-bit binary counter).

Module-12 Study experiment 0 hours

12. To study 4-bitALU using IC-74181.

Last Updated: Tuesday, January 24, 2023

Categories

VTU Updates