Laboratory Experiments:
Note: (1)Use discrete components to test and verify the logic gates.
(2) Use FPGA/CPLD kits for down loading the Verilog code and test the output.
1.Simplification, realization of Boolean expressions using logic gates/Universal gates
2.To design and implement a) Adder/Subtractor – Full/half using logic gates. b) 4-bit Parallel Adder/ subtractor using IC 7483.
3.To realize
a) BCD to Excess-3 code conversion and vice versa
b) Binary to Gray code conversion and vice versa
4.To realize
a) 4:1 Multiplexer using gates
b) 1:8 Demux
c) Priority encoder and 3:8 Decoder using IC74138
d) One / Two bit comparator
5.To realize the following flip-flops using NAND Gates
(a) T type (b) JK Master slave (c) D type
6.To realize the 3-bit counters as a sequential circuit and Mod-N Counter design (7476, 7490, 74192, 74193)
7.Adder/Subtractor – Full/half using Verilog data flow description
8.Code converters using Verilog Behavioral description
a) Gray to binary and vice versa
b) Binary to excess3 and vice versa
9.Multiplexers/decoders/encoder using Verilog Behavioral description
-8:1 mux, 3:8 decoder, 8:3 encoder, Priority encoder
- 1:8 Demux and verify using test bench
- 2-bit Comparator using behavioral description
10.Flip-flops using Verilog Behavioral description
a) JK type b) SR type c) T type and d) D type
11.Counter up/down (BCD and binary), sequential counters using Verilog Behavioral description.
12. Interface experiments: (a) Stepper motor (b) Relay (c) Waveform generation using DAC.
Course Outcomes:
After studying this course, students will able to:
• Realize Boolean expression using Universal gates / basic gates using ICs and Verilog
• Demonstrate the function of adder/subtractor circuits using gates/ICs & Verilog.
• Design and analyze the Comparator, Multiplexers Decoders, Encoders circuits using ICs and Verilog.
• Design and analysis of different Flip-flops and counters using gates and FFs
• Able to use FPGA/CPLD kits for down loading Verilog codes for shift registers and counters and check output.
Conduct of Practical Examination:
1. All laboratory experiments are to be included for practical examination.
2. Students are allowed to pick one experiment from the lot.
3. Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
4. Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero
Reference Books:
1. Digital Principles and Design – Donald D Givone,12th reprint, TMH,2008
2. HDL Programming VHDL and Verilog By Nazeih M. Botros, 2009 reprint, Dreamtech press.
3. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001
4. Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010.